1. Field of the Invention
The present invention relates to a semiconductor integrated circuit layout method, more particularly to a method of placing capacitors and transistors to provide protection from plasma damage and electrostatic discharge.
2. Description of the Related Art
Modern semiconductor integrated circuit fabrication processes include many deposition and etching steps involving the use of plasma. A resulting problem is that the electrical charge of the plasma, conducted through metal and other conductive patterns in the integrated circuit, can damage internal parts of the integrated circuit during the fabrication process. Particularly vulnerable to such plasma damage are the thin oxide films that insulate the gate electrodes of transistors from the substrate in which the transistors are formed.
The risk of plasma damage depends on what is referred to as the antenna ratio. For the semiconductor integrated circuit as a whole, the antenna ratio is the ratio of the total area occupied by metal patterns, which act as antennas for receiving plasma charge, to the total area of the gate electrodes, excluding metal patterns not electrically coupled to any gate electrode. For a particular gate electrode, the antenna ratio is the ratio of the total area of the metal patterns electrically coupled to the gate electrode to the total area of the gate electrodes electrically coupled to those metal patterns. A high antenna ratio implies that much charge will be concentrated on the gate electrodes during plasma processing.
Gate electrodes that are connected to the power supply pattern or ground pattern tend to have an especially high antenna ratio, due to the large size of the power and ground patterns. Such gate electrodes are found in transistors used for current limitation. Ironically, such gate electrodes are also found in protection transistors that are intended to protect internal circuitry from electrostatic discharge.
A known method of reducing the risk of plasma damage is to provide additional capacitors to absorb the plasma charge. The problem is where to place the capacitors. Japanese Unexamined Patent Application Publication No. 11-168196 suggests placing capacitors beneath the pads used for external signal connections, or beneath the interconnecting lines leading from these pads to the gate electrodes. This scheme, however, requires a separate capacitor for each gate electrode, and fails to provide capacitors for gate electrodes that do not receive external signals. In particular, it does not adequately protect the gate electrodes of current limiting transistors and protection transistors, which are most vulnerable to plasma damage.
A further problem that afflicts semiconductor integrated circuits is variations in the power supply and ground potentials caused by switching of output signals between the high and low logic levels, especially when a large number of outputs are switched simultaneously. This problem is generally known as ground bounce.